[Rpm-maint] [rpm-software-management/rpm] Add znver1 arches with 32-bit + 64-bit variants and proper CPU detection (#1035)

[Panu Matilainen]

I'm just really, really weary and dubious about these architecture tweaks because they're so bleeping arbitrary. Looking at gcc manual around znver:

          znver1
               AMD Family 17h core based CPUs with x86-64 instruction set
               support.  (This supersets BMI, BMI2, F16C, FMA, FSGSBASE, AVX,
               AVX2, ADCX, RDSEED, MWAITX, SHA, CLZERO, AES, PCL_MUL, CX16,
               MOVBE, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM,
               XSAVEC, XSAVES, CLFLUSHOPT, POPCNT, and 64-bit instruction set
               extensions.

           znver2
               AMD Family 17h core based CPUs with x86-64 instruction set
               support. (This supersets BMI, BMI2, ,CLWB, F16C, FMA, FSGSBASE,
               AVX, AVX2, ADCX, RDSEED, MWAITX, SHA, CLZERO, AES, PCL_MUL,
               CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1,
               SSE4.2, ABM, XSAVEC, XSAVES, CLFLUSHOPT, POPCNT, and 64-bit
               instruction set extensions.)

           btver1
               CPUs based on AMD Family 14h cores with x86-64 instruction set
               support.  (This supersets MMX, SSE, SSE2, SSE3, SSSE3, SSE4A,
               CX16, ABM and 64-bit instruction set extensions.)

           btver2
               CPUs based on AMD Family 16h cores with x86-64 instruction set
               support. This includes MOVBE, F16C, BMI, AVX, PCL_MUL, AES,
               SSE4.2, SSE4.1, CX16, ABM, SSE4A, SSSE3, SSE3, SSE2, SSE, MMX
               and 64-bit instruction set extensions.

Why do we need znver when we didn't need btver? Or the million other things that are there - gcc 9.2.1 manual lists no less than 79 cpu types for the x86 family, we know about a dozen. Which is already more than we should, I would say.

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